You can find our final report, block diagram, code, and testbenches in the repository.
The purpose of this project was to create and design the digital logic for a pipelined RISC-V CPU running the RV32I ISA. The design is then to be loaded onto the Xilinx PYNQ-Z1 FPGA. The processor is also equipped with a set of memory-mapped IO that includes three major different memories: BIOS Memory, Data Memory, and Instruction Memory. By interacting with these different memories, users should be able to upload instructions via the memory-mapped UART and execute instructions on the CPU.
We started the design process by creating a block diagram of the CPU, organizing it into a three-stage pipelined processor. We then started creating individual modules for the CPU. As we developed the modules, we simultaneously created testbenches to test the functionality of each module. Once we were satisfied with the functionality of each module, we started to connect the modules together to form the CPU.
We also added a branch predictor that used a direct-mapped cache and saturating counter to help reduce the CPI of branching instructions.
In the end, we tested our CPU by running the provided
mmult.c which performs a series of matrix multiplications. You can also find our results in the final report.